Module 5 Set-3

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#1. Which one of the following gives the length of an ARINC 429 data word:

(a) 16 bits

(b) 32 bits

#3. The inter-frame gap in AFDX is equivalent to:

(a) 17-bit periods

(b) 31-bit periods

#4. Within an AFDX switch each end system is connected by means of:

(a) shared bus cables and shared RX and TX buffers

(b) individual bus cables and shared RX and TX buffers

#6. The typical maximum clock frequency for a standard TTL logic device is:

(a) 2 MHz

(b) 10 MHz

#7. The resolution of a DAC depends on:

(a) the speed at which the device operates

(b) the accuracy of the reference voltage used

#8. Bus arbitration is required in order to:

(a) avoid bus contention

(b) prevent memory loss

#9. Which one of the following gives the range of values that can be indicated by an unsigned byte:

(a) 0 to 255

(b) –128 to +127

#10. How many 16K × 4-bit DRAM devices are needed to provide 64K bytes of storage:

(a) 4

(b) 8

#11. Which one of the following classes of semiconductor device is most susceptible to static voltages:

(a) VLSI microprocessors

(b) bipolar junction transistors

#12. Which one of the following aircraft software applications has the highest level of criticality:

(a) DME

(b) GPS

#13. . In order to minimise the effect of reflections caused by a mismatch, a bus cable should be:

(a) terminated at each end

(b) kept as short as possible

#14. The clock oscillator in a microprocessor system provides:

(a) a sine wave signal of accurately controlled frequency

(b) a square wave signal of accurately controlled frequency

#15. . Real-time monitoring of critical systems is a function of:

(a) BITE

(b) FMS

#16. . In an AFDX network the links from each host to the switch are:

(a) simplex

(b) half-duplex

#17. Within an AFDX network, the ethernet frames associated with a particular virtual link can originate at:

(a) multiple end systems

(b) one, and only one, end system

#18. The hexadecimal number E3 is equivalent to the binary number:

(a) 11100111

(b) 11100011

#19. . In a microprocessor system, faster processing can be achieved by means of:

(a) instruction pipelining

(b) a complex instruction set

#20. The last part of an AFDX frame contains:

(a) the MAC start and destination addresses and VL identifiers

(b) the AFDX payload and sequence number